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cy25404 quad pll programmable clock generator with spread spectrum cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-43258 rev. *c revised july 11, 2011 features four fully integrated phase-locked loops (plls) input frequency range ? external crystal: 8 to 48 mhz ? external reference: 8 to 166 mhz clock wide operating output frequency range ? 3 to 166 mhz programmable spread spectrum with center and down spread option and lexmark and linear modulation profiles selectable v dd supply voltage options: ? 2.5 v, 3.0 v, and 3.3 v selectable output clock voltages, independent of v dd supply: ? 2.5 v, 3.0 v, and 3.3 v frequency select feature with option to select eight different frequencies over nine clock outputs output enable, and ss on/off controls low jitter, high accuracy outputs ability to synthesize nonstandard frequencies with fractional-n capability up to nine clock outputs wit h programmable drive strength glitch-free outputs while frequency switching 20-pin tssop package commercial and industrial temperature ranges benefits multiple high performance plls allow synthesis of unrelated frequencies nonvolatile programming for personalization of pll frequencies, spread spectrum c haracteristics, drive strength, crystal load capacitance, and output frequencies application specific programmable electromagnetic interference (emi) reduction using spread spectrum for clocks programmable plls for system frequency margin tests meets critical timing requirements in complex system designs suitability for pc, consumer, portable, and networking applications capable of zero parts per million (ppm) frequency synthesis error uninterrupted system operati on during clock frequency switch application compatibility in standard and low power systems osc pll1 pll2 pll3 (ss) pll4 (ss) output dividers and drive strength control clk1 clk9 clk8 clk7 clk6 clk5 clk4 clk3 clk2 fs 2 fs 1 fs 0 sson xout xin/ exclkin oe bank 1 bank 3 bank 2 mux and control logic crossbar switch block diagram
cy25404 document #: 001-43258 rev. *c page 2 of 13 contents general description ......................................................... 4 four configurable plls .............................................. 4 input reference clocks .......... .............. .............. ......... 4 v dd power supply options ......................................... 4 output bank settings .................................................. 4 output source selection ............................................. 4 spread spectrum control ............................................ 4 frequency select ........................................................ 4 glitch-free frequency switch ..................................... 4 output enable mode .............. .............. .............. ......... 4 output drive strength .................................................. 4 generic configuration and custom frequency ........... 4 absolute maximum conditions....................................... 5 recommended operating conditions ............................ 5 dc electrical specifications ............................................ 6 recommended crystal specification for smd package .............................................................. 7 recommended crystal specification for thru-hole package ..................................................... 7 ac electrical specifications ............................................ 7 test and measurement setup .......................................... 8 voltage and timing definitions ....................................... 8 ordering information ........................................................ 9 possible configurations ............................................... 9 ordering code definitions ..... ...................................... 9 package drawing and dimensions ............................... 10 acronyms ........................................................................ 11 document conventions ................................................. 11 units of measure ....................................................... 11 document history page ................................................. 12 sales, solutions, and legal information ...................... 13 worldwide sales and design s upport ......... .............. 13 products .................................................................... 13 psoc solutions ......................................................... 13
cy25404 document #: 001-43258 rev. *c page 3 of 13 figure 1. pin diagram - cy25404 20 ld tssop table 1. pin definition - cy25404 (v dd = 2.5 v, 3.0 v or 3.3 v supply) pin number name io description 1v dd power power supply: 2.5 v/3.0 v/3.3 v 2 xout output crystal output 3 xin/exclkin input crystal input or 1.8 v external clock input 4v ss power power supply ground 5 clk1 output programmable clock output. output voltage depends on v dd _clk_b1 voltage 6v dd _clk_b1 power power supply for bank1, (clk 1, clk2, clk3) outputs: 2.5 v/3.0 v/3.3 v 7 clk2 output programmable clock output. output voltage depends on v dd _clk_b1 voltage 8v ss power power supply ground 9 clk3/fs0 output/input multifunction programmable pi n: programmable clock output or frequency select input pin. output voltage of clk3 depends on v dd _clk_b1 voltage 10 oe/fs1 input multifunction programmable pin: hi gh-true output enable or frequency select pin 11 clk4/fs2 output/input multifunction programmable pi n: programmable clock output or frequency select input pin. output voltage of clk4 depends on v dd _clk_b2 voltage 12 clk5 output programmable clock output. output voltage depends on v dd _clk_b2 voltage 13 v ss power power supply ground 14 clk6 output programmable clock output. output voltage depends on v dd _clk_b2 voltage 15 v dd _clk_b2 power power supply for bank2, (clk 4, clk5, clk6) outputs: 2.5 v/3.0 v/3.3 v 16 clk7/sson output/input multifunction programmable pi n. programmable clock output or spread spectrum on/off control input pin. output voltage of clk7 depends on v dd _clk_b3 voltage 17 v dd _clk_b3 power power supply for bank3, (clk 7, clk8, clk9) outputs: 2.5 v/3.0 v/3.3 v 18 clk8 output programmable clock output. output voltage depends on v dd _clk_b3 voltage 19 v ss power power supply ground 20 clk9 output programmable clock output. output voltage depends on v dd _clk_b3 voltage 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 vdd xout xin/exclkin vss clk1 vdd_clk_b1 clk2 vss clk3/fs0 oe/fs1 clk5 clk6 vss clk7/sson vdd_clk_b2 vdd_clk_b3 clk9 vss clk4/fs2 cy25404 11 clk8
cy25404 document #: 001-43258 rev. *c page 4 of 13 general description four configurable plls the cy25404 has four programmable plls that can be used to generate output frequencies ranging from 3 to 166 mhz. the advantage of having four plls is that a single device generates up to four independent frequencies from a single crystal. input reference clocks the input to the cy25404 can be either a crystal or a clock signal. the input frequency range for crystals is 8 mhz to 48 mhz, while that for clock signals is 8 mhz to 166 mhz. the required voltage level for the input reference clock (exclkin) is shown in the dc and ac electrical specification tables. v dd power supply options this device has programmable power supply option and it can be programmed to operate at any voltage 2.5 v, 3.0 v, or 3.3 v. output bank settings there are nine clock outputs grouped in three output driver banks. the bank 1, bank 2, an d bank 3 correspond to (clk1, clk2, clk3), (clk4, clk5, cl k6), and (clk7, clk8, clk9) respectively. separate power supplies are used for each of these banks and they can be any of 2.5 v, 3.0 v, or 3.3 v. these voltages are independent of v dd power supply used, giving user multiple choice of output clock voltage levels. output source selection these devices have programmable input sources for each of its nine clock outputs (clk1?9). there are five available clock sources for these outputs. these clock sources are: xin/exclkin, pll1, pll2, pll3, or pll4. output clock source selection is done using four out of five crossbar switch. thus, any one of these five available clock sources can be arbitrarily selected for the clock outputs. this gives user a flexibility to have up to four independent clock outputs. spread spectrum control two of the four plls (pll3 an d pll4) have spread spectrum capability for emi reduction in the system. the device uses a cypress proprietary pll and spread spectrum clock (ssc) technology to synthesize and modulate the frequency of the pll. the spread spectrum feature can be turned on or off using a multifunction control pin (clk7/sson). it can be programmed to either center spread range from 0.125% to 2.50% or down spread range from ?0.25% to ?5.0% with lexmark or linear profile. frequency select there are three multifunction frequency select pins (fs0, fs1 and fs2) that provide an option to select eight different sets of frequencies among each of the four plls. each output has programmable output divider options. glitch-free frequency switch when the frequency select pin (fs) is used to switch frequency, the outputs are glitch-free prov ided frequency is switched using output dividers. this featur e enables uninterrupted system operation while clock frequency is being switched. output enable mode there is a multifunction programmable pin 10, oe/fs1 that can be programmed to operate as out put enable (oe) mode. oe is a high-true input and individual clock outputs can be programmed to be sensitive to this oe pin. if activated it shuts off the output drivers, resulti ng in minimum power consumption for the device. output drive strength the dc drive strength of the individual clock output can be programmed for different values. table 2 shows the typical rise and fall times for different drive strength settings. generic configuration and custom frequency there is a generic set of output frequencies available from the factory that can be used for the device evaluation purposes. the device, cy25404 can be custom programmed to any desired frequencies and listed features . for customer specific programming, please contact local cypress field application engineer (fae) or sales representative. table 2. output drive strength output drive strength rise/fall time (ns) (typical value) low 6.8 mid low 3.4 mid high 2.0 high 1.0
cy25404 document #: 001-43258 rev. *c page 5 of 13 absolute maximum conditions parameter description condition min max unit v dd supply voltage ? ?0.5 4.5 v v dd_clk_bx output bank supply voltage ? ?0.5 4.5 v v in input voltage relative to v ss ?0.5 v dd +0.5 v t s temperature, storage non functional ?65 +150 c esd hbm esd protection (human body model) j edec eia/jesd22-a114-e 2000 volts ul-94 flammability rating v-0 at 1/8 in. ? 10 ppm msl moisture sensitivity level ? 3 recommended oper ating conditions parameter description min typ max unit v dd v dd operating voltage 2.25 ? 3.60 v v dd_clk_bx output driver voltage for bank 1, 2 and 3 2.25 ? 3.60 v t ac commercial ambient temperature 0 ? +70 c t ai industrial ambient temperature ?40 -- +85 c c load maximum load capacitance ? ? 15 pf t pu power-up time for all v dd to reach minimum specified voltage (power ramps must be monotonic) 0.05 ? 500 ms notes 1. guaranteed by design but not 100% tested. 2. configuration dependent.
cy25404 document #: 001-43258 rev. *c page 6 of 13 dc electrical specifications parameter description conditions min typ max unit v ol output low voltage i ol = 2 ma, drive strength = [00] ? ? 0.4 v i ol = 3 ma, drive strength = [01] i ol = 7 ma, drive strength = [10] i ol = 12 ma, drive strength = [11] v oh output high voltage i oh = ?2 ma, drive st rength = [00] v dd_clk_bx ? 0.4 ??v i oh = ?3 ma, drive strength = [01] i oh = ?7 ma, drive strength = [10] i oh = ?12 ma, drive strength = [11] v il1 input low voltage of fs0, oe/fs1, fs2, and sson ???0.2*v dd v v il2 input low voltage of exclkin ? ? ? 0.18 v v ih1 input high voltage of fs0, oe/fs1, fs2, and sson ?0.8*v dd ??v v ih2 input high voltage of exclkin ? 1.62 ? 2.2 v i il1 input low current of oe/fs1 pin v il = 0v ? ? 10 a i ih1 input high current of oe/fs1 pin v ih = v dd ? ? 10 a i il2 input low current of sson, fs0 and fs2 pins v il = 0v (internal pull dn = 160k typ) ? ? 10 a i ih2 input high current of sson, fs0, and fs2 pins v ih = v dd (internal pull dn = 160k typ) 14 ? 36 a r dn pull down resistor of sson, fs0, and fs2 and off state (clk1-clk9) pins clock outputs in off-state by setting oe = low 100 160 250 k ? i dd [1,2] supply current for cy25404 oe = high, no load ? 22 ? ma c in [1] input capacitance sson, clkin, fs0, oe/fs1, and fs2 pins ?7pf
cy25404 document #: 001-43258 rev. *c page 7 of 13 ac electrical specifications parameter description conditions min typ max unit f in (crystal) crystal frequency, xin ? 8 ? 48 mhz f in (clock) input clock frequency, exclkin ? 8?166mhz f clk output clock frequency ? 3 ? 166 mhz dc1 output duty cycle, all clocks except ref out duty cycle is defined in figure 3 on page 8 ; t 1 /t 2 , measured at 50% of v dd _ clk_bx 45 50 55 % dc2 ref out duty cycle ref in min 45%, max 55% 40 ? 60 % t rf1 [1] output rise/fall time measured from 20% to 80% of v dd _ clk_bx , as shown in figure 4 on page 8 , c load = 15 pf, drive strength [00] ?6.8?ns t rf2 [1] output rise/fall time measured from 20% to 80% of v dd _ clk_bx , as shown in figure 4 on page 8 , c load = 15 pf, drive strength [01] ?3.4?ns t rf3 [1] output rise/fall time measured from 20% to 80% of v dd _ clk_bx , as shown in figure 4 on page 8 , c load = 15 pf, drive strength [10] ?2.0?ns t rf4 [1] output rise/fall time measured from 20% to 80% of v dd _ clk_bx , as shown in figure 4 on page 8 , c load = 15 pf, drive strength [11] ?1.0?ns t ccj [1,2] cycle-to-cycle jitter (peak) configuration dependent. see table 3 ?100? ps t lock [1] pll lock time measured from 90% of the applied power supply level ?13ms table 3. configuration example for c-c jitter ref. freq. (mhz) clk1 output clk2 output clk3 output clk4 output clk5 output freq. (mhz) c-c jitter typ (ps) freq. (mhz) c-c jitter typ (ps) freq. (mhz) c-c jitter typ (ps) freq. (mhz) c-c jitter typ (ps) freq. (mhz) c-c jitter typ (ps) 14.3181 8.0 134 166 103 48 92 74.25 81 not used 19.2 74.25 99 166 94 8 91 27 110 48 75 27 48 67 27 109 166 103 74.25 97 not used 48 48 93 27 123 166 137 166 138 8 103 recommended crystal spec ification for smd package parameter description range 1 range 2 range 3 unit f in crystal frequency 8 ? 14 14 ? 28 28 ? 48 mhz r1 maximum motional resistance (esr) 135 50 30 ? cl parallel load capacitance (device has internal load capacitance adjustment feature) 8 ? 18 8 ? 14 8 ? 12 pf dl(max) maximum crystal drive level 300 300 300 w recommended crystal specific ation for thru-hole package parameter description range 1 range 2 range 3 unit f in crystal frequency 8 ? 14 14 ? 24 24 ? 32 mhz r1 maximum motional resistance (esr) 90 50 30 ? cl parallel load capacitance (device has internal load capacitance adjustment feature) 8 ? 18 8 ? 12 8 ? 12 pf dl(max) maximum crystal drive level 1000 1000 1000 w
cy25404 document #: 001-43258 rev. *c page 8 of 13 test and measurement setup figure 2. test and measurement setup voltage and timing definitions figure 3. duty cycle definition figure 4. rise time = t rf , fall time = t rf 0.1 ? f v dd outputs c load gnd dut clock output v dd_clk_b x 50% of v dd_clk_b x 0v t 1 t 2 clock output t rf t rf v dd_clk_bx 80% of v dd_clk_bx 20% of v dd_clk_bx 0v
cy25404 document #: 001-43258 rev. *c page 9 of 13 ordering code definitions ordering information some product offerings are factory programmed customer sp ecific devices with customized part numbers. the possible configurations table shows the available dev ice types, but not complete part numbers. contact your local cypress fae or sales representative for more information. possible configurations part number [3] type production flow pb-free cy25404zxc-xxx 20-pin tssop commercial, 0 c to 70 c cy25404zxc-xxxt 20-pin tssop -tape and reel commercial, 0 c to 70 c CY25404ZXI-XXX 20-pin tssop industrial, ?40 c to +85 c CY25404ZXI-XXXt 20-pin tssop -tape and reel industria l, ?40 c to +85 c note 3. xxx indicates factory programmable and are factory programmed c onfigurations. for more details, contact your local cypress fa e or cypress sales representative. package type: (t = tape and reel) customer specific identification code temperature code (c= commercial or i= industrial) 20-pin tssop package marketing code: cy25404 = device number zx c/i - xxx t cy25404
cy25404 document #: 001-43258 rev. *c page 10 of 13 package drawing and dimensions figure 5. 20-ld tssop, thin shrunk small outline package (4.40 mm body) zz2 51-85118 *c
cy25404 document #: 001-43258 rev. *c page 11 of 13 acronyms document conventions units of measure acronym description dl drive level emi electromagnetic interference esd electrostatic discharge fae field application engineer fs frequency select jedec eia joint electron devices engineering council electronic industries alliance oe output enable osc oscillator pd power-down pll phase-locked loop ppm parts per million ss spread spectrum ssc spread spectrum clock sson spread spectrum on tssop thin shrunk small outline package symbol unit of measure c degrees celsius ff femtofarads ma milliampere mhz megahertz ? s microseconds ms millisecond ? w microwatts ns nanoseconds pf picofarads ppm parts per million ps picoseconds v volts ? ohms w watts
cy25404 document #: 001-43258 rev. *c page 12 of 13 document history page document title: cy25404 quad pll programmable clock generator with spread spectrum document number: 001-43258 rev. ecn no. issue date orig. of change description of change ** 1793805 see ecn dpf/aesa new data sheet *a 2748211 08/10/09 tsai posting to external web. *b 2899300 03/26/2010 cxq updated ordering informati on. added note regarding possible configura- tions in ordering information section. added possible configurations table for ?xxx? parts. updated package drawing and dimensions *c 3308261 07/11/2011 bash added ordering code definitions updated package drawing and dimensions added acronyms added units of measure added contents
document #: 001-43258 rev. *c revised july 11, 2011 page 13 of 13 cy25404 ? cypress semiconductor corporation, 2007-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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